The 320C6201B DSP is a member of the fixed-point DSP family in the 320C6000 platform. The SM/SMJ320C6201B (C6201B) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI™), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1600 million instructions per second (MIPS) at a clock rate of 200 MHz, the C6201B offers cost-effective solutions to high-performance DSP programming challenges. The C6201B is a newer revision of the C6201. The C6201B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6201B can produce two multiply-accumulates (MACs) per cycle - for a total of 400 million MACs per second (MMACS). The C6201B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6201B includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory of the C6201B consists of two 32K-byte blocks of RAM for improved concurrency. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C6201B has a complete set of development tools which includes: a new C compiler, a third-party Ada 95 compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

• Highest Performance Fixed-Point Digital Signal Processor (DSP) SM/SMJ320C6201B
  • 5-, 6.7-ns Instruction Cycle Time
  • 150 and 200-MHz Clock Rate
  • Eight 32-Bit Instructions/Cycle
  • 1200 and 1600 MIPS
• VelociTI™ Advanced Very Long Instruction Word (VLIW) C62x™ CPU Core
  • Eight Independent Functional Units:
    • Six ALUs (32-/40-Bit)
    • Two 16-Bit Multipliers (32-Bit Results)
  • Load-Store Architecture With 32 32-Bit General-Purpose Registers
  • Instruction Packing Reduces Code Size
  • All Instructions Conditional
• Instruction Set Features
  • Byte-Addressable (8-, 16-, 32-Bit Data)
  • 32-Bit Address Range
  • 8-Bit Overflow Protection
  • Saturation
  • Bit-Field Extract, Set, Clear
  • Bit-Counting
  • Normalization
• 1M-Bit On-Chip SRAM
  • 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
  • 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency
• 32-Bit External Memory Interface (EMIF)
  • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
  • Glueless Interface to Asynchronous Memories: SRAM and EPROM
• Four-Channel Bootloading Direct-Memory-Access (DMA) Controller with an Auxiliary Channel
• 16-Bit Host-Port Interface (HPI)
  • Access to Entire Memory Map
• Two Multichannel Buffered Serial Ports (McBSPs)
  • Direct Interface to T1/E1, MVIP, SCSA Framers
  • ST-Bus-Switching Compatible
  • Up to 256 Channels Each
  • AC97-Compatible
  • Serial Peripheral Interface (SPI) Compatible (Motorola™)
• Two 32-Bit General-Purpose Timers
• Flexible Phase-Locked Loop (PLL) Clock Generator
• IEEE-1149.1 (JTAG ) Boundary-Scan Compatible
• 429-Pin BGA Package (GLP Suffix)
• CMOS Technology
  • 0.18-um/5-Level Metal Process
• 3.3-V I/Os, 1.8-V Internal

C62x and VelociTI are trademarks of Texas Instruments Incorporated. Motorola is a trademark of Motorola, Inc. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. TI is a trademark of Texas Instruments Incorporated. Windows is a registered trademark of the Microsoft Corporation.