SN54LS193-SP - 同步 4 位加/减计数器（具有双时钟和清零功能）

SN54LS193-SP是TI德州仪器公司的一款计数器/算术/奇偶校验功能产品，SN54LS193-SP是同步 4 位加/减计数器（具有双时钟和清零功能），本站介绍了SN54LS193-SP的封装应用图解、特点和优点、功能等，并给出了与SN54LS193-SP相关的TI元器件型号供参考。

SN54LS193-SP - 同步 4 位加/减计数器（具有双时钟和清零功能） - 计数器/算术/奇偶校验功能 - 特殊逻辑 - 德州仪器

产品描述

These monolithic circuits are synchronous reversible (up/down) counters having a complexity of 55 equivalent gates. The '192 and 'LS192 circuits are BCD counters and the '193 and 'LS193 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple-clock) counters.

The outputs of the four master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is high.

All four counters are fully programmable; that is, each output may be preset to either level by entering the desired data at the data inputs while the load input is low. The output will change to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.

A clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function is independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements. This reduces the number of clock drivers etc., required for long words.

These counters are designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up- and down-counting functions. The borrow output produces a pulse equal in width to the count-down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count-up input when an overflow condition exists. The counters can then be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs respectively of the succeeding counter.

产品特性

Cascading Circuitry Provided Internally
Synchronous Operation
Individual Preset to Each Flip-Flop
Fully Independent Clear Input

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