SN54S181 - 算术逻辑部件/功能生成器

SN54S181是TI德州仪器公司的一款计数器/算术/奇偶校验功能产品，SN54S181是算术逻辑部件/功能生成器，本站介绍了SN54S181的封装应用图解、特点和优点、功能等，并给出了与SN54S181相关的TI元器件型号供参考。

SN54S181 - 算术逻辑部件/功能生成器 - 计数器/算术/奇偶校验功能 - 特殊逻辑 - 德州仪器

产品描述

The 'LS181 and 'S181 are arithmetic logic units (ALU)/function generators that have a complexity of 75 equivalent gates on a monolithic chip. These circuits perform 16 binary arithmetic operations on two 4-bit words as shown in Tables 1 and 2. These operations are selected by the four function-select lines (S0, S1, S2, S3) and include addition, subtraction, decrement, and straight transfer. When performing arithmetic manipulations, the internal carries must be enabled by applying a low-level voltage to the mode control input (M). A full carry look-ahead scheme is made available in these devices for fast, simultaneous carry generation by means of two cascade-outputs (pins 15 and 17) for the four bits in the package. When used in conjunction with the SN54S182 or SN74S182 full carry look-ahead circuits, high-speed arithmetic operations can be performed. The typical addition times shown above illustrate the little additional time required for addition of longer words when full carry look-ahead is employed. The method of cascading 'S182 circuits with these ALUs to provide multi-level full carry look-ahead is illustrated under typical applications data for the 'S182.

If high speed is not of importance, a ripple-carry input (Cn) and a ripple-carry output (Cn+4) are available. However, the ripple-carry delay has also been minimized so that arithmetic manipulations for small word lengths can be performed without external circuitry.

The 'LS181 and 'S181 will accommodate active-high data if the pin designations are interpreted as follows:

Subtraction is accomplished by 1's complement addition where the 1's complement of the subtrahend is generated internally.The resultant output is A – B – 1, which requires an end-around or forced carry to provide A – B.

The 'LS181 or 'S181 can also be utilized as a comparator. The A = B output is internally decoded from the function outputs (F0, F1, F2, F3) so that when two words of equal magnitude are applied at the A and B inputs, it will assume a high level to indicate equality (A = B). The ALU must be in the subtract mode with Cn = H when performing this comparison. The A = B output is open-collector so that it can be wire-AND connected to give a comparison for more than four bits. The carry output (Cn+4) can also be used to supply relative magnitude information. Again, the ALU must be placed in the subtract mode by placing the function select inputs S3, S2, S1, S0 at L, H, H, L, respectively.

These circuits have been designed to not only incorporate all of the designer's requirements for arithmetic operations, but also to provide 16 possible functions of two Boolean variables without the use of external circuitry. These logic functions are selected by use of the four function-select inputs (S0, S1, S2, S3) with the mode-control input (M) at a high level to disable the internal carry. The 16 logic functions are detailed in Tables 1 and 2 and include exclusive-OR, NAND, AND, NOR, and OR functions.

Series 54, 54LS, and 54S devices are characterized for operation over the full military temperature range of -55°C to 125°C; Series 74LS and 74S devices are characterized for operation from 0°C to 70°C.

产品特性

Full Look-Ahead for High-Speed Operations on Long Words
Input Clamping Diodes Minimize Transmission-Line Effects
Darlington Outputs Reduce Turn-Off Time
Arithmetic Operating Modes:
- Addition
- Subtraction
- Shift Operand A One Position
- Magnitude Comparison
- Plus Twelve Other Arithmetic Operations
Logic Function Modes:
- Exclusive-OR
- Comparator
- AND, NAND, OR, NOR
- Plus Ten Other Logic Operations

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