SN65LVDS86A-Q1是TI公司的一款FlatLink/FPD-Link（用于LCD的LVDS）产品，SN65LVDS86A-Q1是汽车类 FlatLink 接收器，本页介绍了SN65LVDS86A-Q1的产品说明、应用、特性等，并给出了与SN65LVDS86A-Q1相关的TI元器件型号供参考。
SN65LVDS86A-Q1 - 汽车类 FlatLink 接收器 - FlatLink/FPD-Link（用于LCD的LVDS） - 显示和成像串行器/解串器 - TI公司（Texas Instruments，德州仪器）
The SN65LVDS86A FlatLink™ receiver contains three serial-in 7-bit parallel-out shift registers and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, ’83, ’84, or ’85, over four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. The SN65LVDS86A presents valid data on the falling edge of the output clock (CLKOUT).
The SN65LVDS86A requires only four line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level.
The SN65LVDS86A is characterized for operation over the full automotive temperature range of –40°C to 125°C.
- 3:21 Data Channel Expansion at up to 178.5Mbytes/s Throughput
- Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI
- Three Data Channels and Clock Low-Voltage Differential Channels In and 21 Data and Clock Low-Voltage TTL Channels Out
- Operates From a Single 3.3-V Supply
- Tolerates 4-kV Human-Body Model (HBM) ESD
- Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch
- Consumes Less Than 1 mW When Disabled
- Wide Phase-Lock Input Frequency Range 31MHz to 68 MHz
- No External Components Required for PLL
- Inputs Meet or Exceed the Standard Requirements of ANSI EIA/TIA-644 Standard
- Improved Replacement for the SN75LVDS86 and NSC DS90C364
- Improved Jitter Tolerance
- Qualified for Automotive Applications
