SN74ACT3651 - 2048 x 36 同步 FIFO 存储器

SN74ACT3651是TI德州仪器公司的一款FIFO寄存器产品，SN74ACT3651是2048 x 36 同步 FIFO 存储器，本站介绍了SN74ACT3651的封装应用图解、特点和优点、功能等，并给出了与SN74ACT3651相关的TI元器件型号供参考。

SN74ACT3651 - 2048 x 36 同步 FIFO 存储器 - FIFO寄存器 - 触发器/锁存器/寄存器 - 德州仪器

产品描述

The SN74ACT3651 is a high-speed, low-power, CMOS clocked FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 11 ns. The 2048 × 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port takes place with two 36-bit mailbox registers. Each mailbox register has a flag that signals when new mail has been stored. Two or more devices are used in parallel to create wider data paths. Expansion is also possible in word depth.

The SN74ACT3651 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control.

The input-ready (IR) flag and almost-full (AF\) flag of the FIFO are two-stage synchronized to CLKA. The output-ready (OR) flag and almost-empty (AE\) flag of the FIFO are two-stage synchronized to CLKB. Offset values for AF\ and AE\ are programmed from port A or through a serial input.

The SN74ACT3651 is characterized for operation from 0°C to 70°C.

For more information on this device family, see the following application reports: FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering (literature number SCAA009) FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) Metastability Performance of Clocked FIFOs (literature number SCZA004)

产品特性

Free-Running CLKA and CLKB Can Be Asynchronous or Coincident
Clocked FIFO Buffering Data From Port A to Port B
Synchronous Read-Retransmit Capability
Mailbox Register in Each Direction
Programmable Almost-Full and Almost-Empty Flags
Microprocessor Interface Control Logic
Input-Ready and AF\ Flags Synchronized by CLKA
Output-Ready and AE\ Flags Synchronized by CLKB
Low-Power 0.8-um Advanced CMOS Technology
Supports Clock Frequencies up to 67 MHz
Fast Access Times of 11 ns
Pin-to-Pin Compatible With SN74ACT3631 and SN74ACT3641
Package Options Include 120-Pin Thin Quad Flat (PCB) and 132-Pin Plastic Quad Flat (PQ) Packages

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