SN74ALS166 - 并联负载 8 位串行移位寄存器

SN74ALS166是TI德州仪器公司的一款移位寄存器产品，SN74ALS166是并联负载 8 位串行移位寄存器，本站介绍了SN74ALS166的封装应用图解、特点和优点、功能等，并给出了与SN74ALS166相关的TI元器件型号供参考。

SN74ALS166 - 并联负载 8 位串行移位寄存器 - 移位寄存器 - 触发器/锁存器/寄存器 - 德州仪器

产品描述

The SN74ALS166 parallel-load 8-bit shift register is compatible with most other TTL logic families. All inputs are buffered to lower the drive requirements. Input clamping diodes minimize switching transients and simplify system design.

These parallel-in or serial-in, serial-out registers have a complexity of 77 equivalent gates on the chip. They feature gated clocks (CLK and CLK INH) inputs and an overriding clear (CLR\) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD\) input. When high, SH/LD\ enables the serial data (SER) input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data (A-H) inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of the clock pulse through a two-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running and the register can be stopped on command with the clock input. CLK INH should be changed to the high level only when CLK is high. The buffered CLR\ overrides all other inputs, including CLK, and sets all flip-flops to zero.

The SN74ALS166 is characterized for operation from 0°C to 70°C.

产品特性

Synchronous Load
Direct Overriding Clear
Parallel-to-Serial Conversion
Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages and Standard Plastic (N) DIP

下面可能是您感兴趣的TI德州仪器公司移位寄存器元器件

TI公司产品现货专家，订购TI公司产品不限最低起订量，TI芯片大陆现货即时发货，香港库存3-5天发货，海外库存7-10天发货

寻找全球TI代理商现货货源 - TI公司（德州仪器）电子元件在线订购