SN74AUP2G80 - 低功耗双路上升沿 D 类触发器

SN74AUP2G80是TI德州仪器公司的一款无产品，SN74AUP2G80是低功耗双路上升沿 D 类触发器，本站介绍了SN74AUP2G80的封装应用图解、特点和优点、功能等，并给出了与SN74AUP2G80相关的TI元器件型号供参考。

SN74AUP2G80 - 低功耗双路上升沿 D 类触发器 - 无 - 小尺寸逻辑器件 - 德州仪器

产品描述

产品特性

Available in the Texas Instruments NanoStar™ Package
Low Static-Power Consumption (ICC = 0.9 µA Maximum)
Low Dynamic-Power Consumption (Cpd = 4.3 pF Typ at 3.3 V)
Low Input Capacitance (Ci = 1.5 pF Typical)
Low Noise – Overshoot and Undershoot <10% of VCC
Ioff Supports Partial-Power-Down Mode Operation
Wide Operating VCC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
tpd = 4.4 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-B, Class II)
- 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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