• Maximum Sample Rate: 80 MSPS/14-Bit
• High Signal-to-Noise Ratio
  • 75.5-dBFS SNR at 5 MHz / 80 MSPS
  • 78.2-dBFS SNR at 5 MHz / 80 MSPS and Decimation Filter Enabled
  • 84-dBc SFDR at 5 MHz / 80 MSPS
• Low Power Consumption
  • 58 mW/CH at 50 MSPS
  • 77 mW/CH at 80 MSPS (2-LVDS Wire Per Channel)
• Digital Processing Block
  • Programmable FIR Decimation Filter and Oversampling to Minimize Harmonic Interference
  • Programmable IIR High-Pass Filter to Minimize DC Offset
  • Programmable Digital Gain: 0 dB to 12 dB
  • 2-Channel or 4-Channel Averaging
• Flexible Serialized LVDS Outputs:
  • One or Two Wires of LVDS Output Lines Per Channel Depending on ADC Sampling Rate
  • Programmable Mapping Between ADC Input Channels and LVDS Output Pins-Eases Board Design
  • Variety of Test Patterns to Verify Data Capture by FPGA/Receiver
• Internal and External References
• 1.8-V Operation for Low Power Consumption
• Low-Frequency Noise Suppression
• Recovery From 6-dB Overload Within 1 Clock Cycle
• Package: 12-mm × 12-mm 80-Pin QFP

• Ultrasound and Sonar Imaging
• Communication Applications
• Multi-channel Data Acquisition

The ADS5294 is a low-power 80-MSPS 8-Channel ADC that uses CMOS process technology and innovative circuit techniques. Low power consumption, high SNR, low SFDR, and consistent overload recovery allow users to design high-performance systems.

The digital processing block of the ADS5294 integrates several commonly used digital functions for improving system performance. The device includes a digital filter module that has built-in decimation filters (with lowpass, highpass and bandpass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This rate is useful for narrow-band applications, where the filters are used to conveniently improve SNR and knock-off harmonics, while at the same time reducing the output data rate. The device includes an averaging mode where two channels (or even four channels) are averaged to improve SNR.