DS90CF386是TI公司的一款FlatLink/FPD-Link（用于LCD的LVDS）产品，DS90CF386是+3.3V LVDS 接收器 24 位平板显示 (FPD) 链接 - 85 MHz，本页介绍了DS90CF386的产品说明、应用、特性等，并给出了与DS90CF386相关的TI元器件型号供参考。
DS90CF386 - +3.3V LVDS 接收器 24 位平板显示 (FPD) 链接 - 85 MHz - FlatLink/FPD-Link（用于LCD的LVDS） - 显示和成像串行器/解串器 - TI公司（Texas Instruments，德州仪器）
The DS90CF386 receiver converts the four LVDS data streams (Up to 2.38 Gbps throughput or 297.5 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also available is the DS90CF366 that converts the three LVDS data streams (Up to 1.78 Gbps throughput or 223 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both Receivers' outputs are Falling edge strobe. A Rising edge or Falling edge strobe transmitter (DS90C385/DS90C365) will interoperate with a Falling edge strobe Receiver without any translation logic.
The DS90CF386 is also offered in a 64 ball, 0.8mm fine pitch ball grid array (NFBGA) package which provides a 44 % reduction in PCB footprint compared to the 56L TSSOP package.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
- 20 to 85 MHz Shift Clock Support
- Rx Power Consumption <142 mW (typ) @85MHz Grayscale
- Rx Power-Down Mode <1.44 mW (max)
- ESD Rating >7 kV (HBM), >700V (EIAJ)
- Supports VGA, SVGA, XGA and Single Pixel SXGA.
- PLL Requires No External Components
- Compatible with TIA/EIA-644 LVDS Standard
- Low Profile 56-Lead or 48-lead TSSOP Package
- DS90CF386 Also Available in a 64 Ball, 0.8mm Fine Pitch Ball Grid Array (NFBGA) Package
