SN5497 - 同步 6 位二进制比率乘法器

SN5497是TI德州仪器公司的一款比率乘法器/分频器/定时器产品，SN5497是同步 6 位二进制比率乘法器，本站介绍了SN5497的封装应用图解、特点和优点、功能等，并给出了与SN5497相关的TI元器件型号供参考。

SN5497 - 同步 6 位二进制比率乘法器 - 比率乘法器/分频器/定时器 - 特殊逻辑 - 德州仪器

产品描述

These monolithic, fully synchronous, programmable counters utilize Series 54/74 TTL circuitry to achieve 32-megahertz typical maximum operating frequencies. These six-bit serial binary counters feature buffered clock, clear, and enable inputs to control the operation of the counter, and a strobe input to enable or inhibit the rate input/decoding AND-OR-INVERT gates. The outputs have additional gating for cascading and transferring unity-count rates.

The counter is enabled when the clear, strobe, and enable inputs are low. With the counter enabled, the output frequency is equal to the input frequency multiplied by the rate input M and divided by 64, ie.:

When the rate input is binary 0 (all rate inputs low), Z remains high. In order to cascade devices to perform 12-bit rate multiplication, the enable output is connected to the enable and strobe inputs of the next stage, the Z output of each stage is connected to the unity/cascade input of the other stage, and the sub-multiple frequency is taken from the Y output.

The unity/cascade input, when connected to the clock input, may be utilized to pass the clock frequency (inverted) to the Y output when the rate input/decoding gates are inhibited by the strobe. The unity/cascade input may also be used as a control for the Y output.

产品特性

Perform Fixed-Rate or Variable-Rate Frequency Division
For Applications in Arithmetic, Radar, Digital-to-Analog (D/A), Analog-to-Digital (A/D), and other Conversion Operations
Typical Maximum Clock Frequency … 32 Megahertz

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