SN74ALVCH162601是TI公司的一款通用总线收发器(UBT)产品，SN74ALVCH162601是具有三态输出的 18 位通用总线收发器，本页介绍了SN74ALVCH162601的产品说明、应用、特性等，并给出了与SN74ALVCH162601相关的TI元器件型号供参考。
SN74ALVCH162601 - 具有三态输出的 18 位通用总线收发器 - 通用总线收发器(UBT) - 通用总线功能 - TI公司（Texas Instruments，德州仪器）
This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH162601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, CLKBA, and CLKENBA\.
The B-port outputs include equivalent 26- series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162601 is characterized for operation from –0°C to 85°C.
- Member of the Texas Instruments Widebus™ Family
- EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
- UBT™ (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes
- B-Port Outputs Have Equivalent 26- Series Resistors, So No External Resistors Are Required
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages
NOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR. Widebus, EPIC, UBT are trademarks of Texas Instruments.
