SN74LVCE161284 - 具有无错上电的 19 位 IEEE 1284 转换收发器

SN74LVCE161284是TI德州仪器公司的一款IEEE-1284并行端接口(PPI)产品，SN74LVCE161284是具有无错上电的 19 位 IEEE 1284 转换收发器，本站介绍了SN74LVCE161284的封装应用图解、特点和优点、功能等，并给出了与SN74LVCE161284相关的TI元器件型号供参考。

SN74LVCE161284 - 具有无错上电的 19 位 IEEE 1284 转换收发器 - IEEE-1284并行端接口(PPI) - 特殊逻辑 - 德州仪器

产品描述

The SN74LVCE161284 is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control input (DIR) is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side, and four receivers. The SN74LVCE161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

The Y outputs (Y9–Y13) stay in the high state after power on until an associated input (A9–A13) goes high. When an associated input goes high, all Y outputs are activated, and noninverting signals of the associated inputs are driven through Y outputs. This special feature prevents printer-system errors caused by deasserting the BUSY signal in the cable at power on.

产品特性

Auto-Power-Up Feature Prevents Printer Errors When Printer Is Turned On, But No Valid Signal Is at A9–A13 Pins
1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
Designed for the IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications
Flow-Through Architecture Optimizes PCB Layout
Ioff and Power-Up 3-State Support Hot Insertion
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection
- ±4 kV - Human-Body Model
- ±8 kV - IEC 61000-4-2, Contact Discharge (Connector Pins)
- ±15 kV - IEC 61000-4-2, Air-Gap Discharge (Connector Pins)
- ±15 kV - Human-Body Model (Connector Pins)

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