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TLC2543-EP - 产品图解:
TLC2543-EP-军用增强型塑料 12 位 66kSPS ADC,具有串行 输出、可编程 MSB/LSB 优先、11 通道
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TI产品 - TLC2543-EP介绍

TLC2543-EP - 军用增强型塑料 12 位 66kSPS ADC,具有串行 输出、可编程 MSB/LSB 优先、11 通道

TLC2543-EP是TI德州仪器公司的一款精密ADC(<=10MSPS)产品,TLC2543-EP是军用增强型塑料 12 位 66kSPS ADC,具有串行 输出、可编程 MSB/LSB 优先、11 通道,本站介绍了TLC2543-EP的封装应用图解、特点和优点、功能等,并给出了与TLC2543-EP相关的TI元器件型号供参考。

TLC2543-EP - 军用增强型塑料 12 位 66kSPS ADC,具有串行 输出、可编程 MSB/LSB 优先、11 通道 - 精密ADC(<=10MSPS) - 模数转换器 - 德州仪器

产品描述
产品特性

  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of -40°C to 125°C (TLC2543Q) and -55°C to 125°C (TLC2543M)
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification
  • Qualification Pedigree(1)
  • 12-Bit-Resolution Analog-to-Digital Converter (ADC)
  • 10-µs Conversion Time Over Operating Temperature
  • 11 Analog Input Channels
  • Three Built-In Self-Test Modes
  • Inherent Sample-and-Hold Function
  • Linearity Error . . . ±1 LSB Max
  • On-Chip System Clock
  • End-of-Conversion (EOC) Output
  • Unipolar or Bipolar Output Operation (Signed Binary With Respect to 1/2 the Applied Voltage Reference)
  • Programmable Most Significant Bit (MSB) or Least Significant Bit (LSB) First
  • Programmable Power Down
  • Programmable Output Data Length
  • CMOS Technology
  • Application Report Available(2)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.(2) Microcontroller Based Data Acquisition Using the TLC2543 12-bit Serial-Out ADC (SLAA012)

DESCRIPTION/ORDERING INFORMATION

The TLC2543 is a 12-bit, switched-capacitor, successive-approximation, analog-to-digital converter (ADC). This device, with three control inputs [chip select (CS), input-output clock (I/O CLOCK), and address input (DATA INPUT)], is designed for communication with the serial port of a host processor or peripheral through a serial 3-state output. The device allows high-speed data transfers from the host.

In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel multiplexer that can select any 1 of 11 inputs or any 1 of 3 internal self-test voltages. The sample-and-hold function is automatic. At the end of conversion, the end-of-conversion (EOC) output goes high to indicate that conversion is complete. The converter incorporated in the device features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating temperature range.

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